(a) Field of the Invention
The present invention relates to a method for fabricating a bipolar transistor having self-aligned base and emitter. The present invention also relates to such a semiconductor device.
(b) Description of the Related Art
Semiconductor deices including therein bipolar transistors have been developed to achieve higher-speed and higher-performance operation. This development is attempted by using finer patterning techniques, wherein the parasitic capacitance and the base resistance of the bipolar transistor are reduced while reducing the junction depth thereof to thereby reduce the transit time of the carriers. One of such patterning techniques is a self-alignment fabrication technique for a bipolar transistor, wherein the emitter region and the base region are separated in a self-alignment scheme, and impurities are introduced from the base lead electrode formed in the periphery of the bipolar transistor to form an external base (or graft base) on the outer periphery of the base region.
In a bipolar transistor having such a self-alignment structure, it is important to reduce the effective emitter width for obtaining excellent high-frequency characteristics such as a steep cut-off frequency (fT) and a high oscillation frequency (fmax). In addition, it is also important not to form a void in a polysilicon layer connected to the emitter region and in the emitter lead electrode connected to the polysilicon layer, thereby obtaining high reliability and a lower emitter resistance of the bipolar transistor.
For example, in order to obtain an excellent oscillation property for a self-aligned bipolar transistor used in a LC oscillator, a higher breakdown voltage (BVebo) should be achieved therein because forward bias and reverse bias are alternately applied in the emitter-base junction. In addition, low-frequency noise should be removed in the self-aligned bipolar transistor if it is used in a voltage controlled oscillator.
FIGS. 14 to 18 consecutively show steps of a conventional fabrication process for a semiconductor device having a self-aligned bipolar transistor. As shown in FIG. 14, the process begins with a silicon substrate 101 on which a first silicon oxide film 102 is formed by a thermal oxidation technique, followed by selectively etching a portion of the first silicon oxide film 102 on the emitter region (region for forming the emitter) and the intrinsic base region (region for forming the intrinsic base 108) by using a photolithographic technique. Subsequently, a first polysilicon layer 103 is deposited on the first silicon oxide film 102 by using a CVD technique, followed by implanting boron ions into the first polysilicon layer 103 by using an ion-implantation technique.
Thereafter, the first polysilicon layer 103 is selectively etched using a photolithographic technique, followed by deposition of a first silicon nitride film 104 by using a CVD technique on both the first polysilicon layer 103 and the first silicon oxide film 102 exposed from the etched first polysilicon layer 103. Subsequently, the first polysilicon layer 103 and the first silicon nitride film 104 are selectively etched to form an opening 105 which exposes the base region other than a graft base region.
Subsequently, a second silicon oxide film 106 is formed using a thermal oxidation technique on the wall and the bottom of the opening 105, the second silicon oxide film 106 serving as a diffusion assist layer. Thereafter, boron ions are implanted through the bottom of the second silicon oxide film 106 into the silicon substrate 101 by using an ion-implantation technique, thereby forming an intrinsic base 108. A second silicon nitride film 107 is then deposited in the opening 105 by using a CVD technique, followed by depositing a second polysilicon layer 110 on the first silicon nitride film 104 in the opening 105, as shown in FIG. 14.
Subsequently, as shown in FIG. 15, the second polysilicon layer 110 is selectively removed by an anisotropic dry etching technique, to leave a first side-wall polysilicon layer 110a on the second silicon nitride film 107 in the opening 105. The anisotropic dry etching is conducted using reactive ions under the gas ambient wherein the etch rate for the polysilicon layer is larger compared to the etch rate for the silicon nitride film. The gas ambient is such that Cl2, HBr and He are introduced at flow rates of 5 to 50 sccm (standard cubic centimeters), 10 to 100 sccm and 1 to 10 sccm, respectively, for example.
During the anisotropic dry etching step, the ions reflected by the first side-wall polysilicon layer 110a in the opening 105 are concentrated on the bottom of the inner side of the polysilicon layer 110a, thereby increasing the etched amount of the bottom of the opening 105 to form a trench 111 on the bottom. The trench 111 may penetrate the second silicon nitride film 107 to reach the second silicon oxide film 106, as shown in FIG. 15. Although the thick second silicon nitride film 107 reduces the aspect ratio of the opening 105 for preventing occurrence of voids in the polysilicon layer etc, in the opening 105, sufficient over-etching is not conducted for the thick second silicon nitride film 107 for avoiding a larger depth for the trench 111.
Subsequently, as shown in FIG. 16, another anisotropic dry etching process is conducted using the first side-wall polysilicon layer 110a as a mask to remove a portion of the second silicon nitride film 107 on the emitter region. The gas ambient in the another anisotropic dry etching is such that the etch rate for the silicon nitride film is larger than the etch rate for the silicon oxide film. For example, SF6 and He are introduced during the another anisotropic dry etching at flow rates of 40 to 200 sccm and 50 to 250 sccm, respectively, while using reactive ions. The another dry etching increases the depth of the trench 111 to form a deep trench 111a, which penetrates the second silicon oxide film 106 to reach the intrinsic base 108.
Subsequently, wet etching is conducted using a mixture of HF, HNO3 and CH3COOH to remove the first side-wall polysilicon layer 110a within the opening 105, further increasing the depth of the trench 111a which has already reached the intrinsic base 108.
Subsequently, as shown in FIG. 17, a portion of the second silicon oxide film 106 on the emitter region is removed by wet etching using a hydrofluoric acid based liquid. Thereafter, the native oxide film on the intrinsic base region is removed by using a hydrofluoric acid based liquid, followed by depositing a second polysilicon layer 113 while introducing SiH4 gas into the deposition chamber. Arsenic ions are then introduced into the second polysilicon layer 113 by using an ion-implantation technique.
Subsequently, an emitter injection treatment is conducted wherein an emitter 114 is formed by diffusing the arsenic ions in the third polysilicon layer 113 toward the intrinsic base 108 by solid phase diffusion. In this emitter injection treatment, although the trench 111a filled with the third polysilicon layer 113 does not penetrate the intrinsic base 108, there is some possibility depending on the process conditions that the diffused ions allow the trench 111a to electrically penetrate the intrinsic base 108 while diffusing toward the silicon substrate 101 which constitutes the collector. Thereafter, a portion of the second polysilicon layer 113 is selectively removed.
Subsequently, as shown in FIG. 18, a first interlayer dielectric film 115 is formed on the first silicon nitride film 104 and the second polysilicon layer 113, followed by selectively etching thereof on the second polysilicon layer 113 and forming consecutively an emitter barrier metal layer 119 having a hollow cylindrical shape and an emitter lead electrode 120 having a solid cylindrical shape.
Further, an emitter electrode 121 having a planar size larger than the planar size of the emitter barrier metal layer 119 is formed on top of the emitter lead electrode 120. Similarly, a base barrier metal layer 116, a base lead electrode 117 and a base electrode 118 as well as a collector barrier metal layer 122, a collector lead electrode 123 and a collector electrode 124 are formed to obtain the structure of the bipolar transistor shown in FIG. 18.
In the conventional fabrication process for the bipolar transistor as described above, if the trench 111a electrically penetrates the intrinsic base 108, a short circuit failure occurs between the collector and the emitter to prevent a normal device operation of the bipolar transistor. Even if the trench 111a does not electrically penetrate the intrinsic base 108, the emitter 114 formed on the planar surface of the intrinsic base 108 does not allow a sufficient large distance between the emitter 114 and the graft base 109. This reduces the breakdown voltage of the emitter-base junction (BVebo) down to as low as 1.8 volts, for example.
Another conventional technique for fabricating a semiconductor device having a bipolar transistor is described in Patent Publication JP-A-2-22827 and a literature entitled xe2x80x9cNARROW BF2 IMPLANTED BASES FOR 35 GHz/24 ps HIGH-SPEED Si BIPOLAR TECHNOLOGYxe2x80x9d in xe2x80x9cIEDM91 Technical Digestxe2x80x9d, pp. 459-462, by K. Ehinger et.al. In this conventional technique, the self-aligned bipolar transistor formed by using an isotropic dry etching for an epitaxial base layer in an opening has a similar problem in that the bipolar transistor has a lower breakdown voltage of the emitter-base junction.
Another conventional technique is also described in Patent Publication JP-A-7-307347. In this conventional technique, the self-aligned bipolar transistor is fabricated by using an isotropic dry etching technique wherein an epitaxial base layer having an opening is etched by a 3 to 9 nm depth. Although the isotropic dry etching used in this technique reduces the damage on the base layer compared to the case of using the anisotropic dry etching, there arises another problem in that the plasma or electrons generated during the isotropic dry etching step generates crystal defects which cause generation and recombination of carriers to thereby increase the low-frequency noise in the resultant bipolar transistor.
Earlier JP Patent Application 2000-071181 also proposes a technique using an isotropic dry etching step in fabrication of the self-aligned bipolar transistor, wherein an epitaxial base layer in an opening is etched. The proposed technique does not remove the damage caused by the isotropic dry etching on the base, although this technique has an advantage in that the electrostatic breakdown voltage can be improved without increasing the base-collector capacitance.
Another conventional technique is described in JP-A-9-172064, wherein the fabrication step for forming the side-wall is conducted twice separately to obtain a two-layer structure for the side-wall in an insulated-gate transistor, such as a longitudinal MOSFET, having a trench. By an anisotropic dry etching using the side-wall having the two-layer structure as a mask, a trench is formed in the silicon substrate by reactive ions.
If the technique described in JP-A-9-172064 is applied to forming a semiconductor device having the self-aligned bipolar transistor, an advantage of smaller effective emitter size may be obtained. In this technique, however, the ions reflected by the wall of the opening in the anisotropic dry etching are concentrated on the bottom edge of the opening to form a trench, similarly to the conventional technique described with reference to FIGS. 14 to 18. The trench may allow the arsenic ions to diffuse and reach the silicon substrate constituting the collector during the emitter injection treatment for forming the emitter, whereby a short-circuit failure occurs between the emitter and the collector and thus a normal device operation cannot be obtained.
In view of the above problems in the conventional techniques, it is an object of the present invention to provide a method for fabricating a semiconductor device having a self-aligned bipolar transistor, which is capable of improving the emitter-base breakdown voltage, preventing the damage of the base layer caused by plasma or electrons such as occurring in the isotropic dry etching, and reducing the low-frequency noise caused by the crystal defects associated with the generation and recombination of carriers.
It is another object of the present invention to provide a method for fabricating a semiconductor device having a self-aligned bipolar transistor, which is suppressing occurrence of a short-circuit failure between the collector and the emitter to obtain a normal device operation.
It is another object of the present invention to provide a semiconductor device having less mount of voids in a polysilicon layer in electric contact with the emitter.
The present invention provides a method for fabricating a bipolar transistor in a semiconductor device, the method including the steps of: forming a silicon layer on a semiconductor substrate; selectively etching the silicon layer to form an opening for exposing a first portion of the semiconductor substrate; conducting a combination etching to the first portion to form a concave surface thereon, the combination etching including consecutive isotropic dry etching and wet etching; implanting first-conductivity type impurities through the concave surface to the first portion to form an intrinsic base; and implanting second-conductivity type impurities into a surface portion of the intrinsic base to form an emitter on the intrinsic base.
In accordance with the method of the present invention, since the damage of the intrinsic base layer caused by the isotropic dry etching is alleviated by the subsequent wet etching, the crystal defects associated with the generation and recombination of carriers can be reduced to thereby suppress the low-frequency noise. The consecutive isotropic dry etching and wet etching allows the bottom surface of the opening having a trench to assume a smooth concave surface. The emitter formed on the concave surface which constitutes the intrinsic base allows a larger distance to be obtained between the central intrinsic base and the peripheral emitter due to the concave surface compared to the distance obtained in the case of the planar surface of the intrinsic base such as in the conventional technique. The larger distance raises the emitter-base breakdown voltage, whereas the concave surface of the intrinsic base alleviates the concentration of the current which has otherwise a tendency to flow the corner of the intrinsic base in the vicinity of the graft base region.
In the present invention, the first and second conductivity types may be p-type and n-type, respectively, or vice versa.
The present invention also provides a semiconductor device including a bipolar transistor having self-aligned emitter and base, the semiconductor device including: a semiconductor substrate; a silicon layer formed on the semiconductor substrate; an opening formed in the silicon layer for exposing an area in which the self-aligned emitter and base are formed; and a side-wall oxide film formed on bottom and wall of the opening.
The semiconductor device of the present invention can be manufactured by the method of the present invention, and achieve the advantages of suppression of occurrence of voids in the silicon layer. The silicon layer may be preferably a polysilicon layer.
The term xe2x80x9cself-aligned bipolar transistorxe2x80x9d as used herein means the structure wherein the opening formed for forming the base of the bipolar transistor is used to define the location of the emitter with respect to the base.